The present invention relates to a semiconductor memory device; and, the invention relates to a technology that is effective for application to a device in which word lines and bit lines connected to dynamic memory cells are respectively divided into plural forms and which has hierarchical word lines and hierarchical IO lines.
As a result of investigations that were carried out subsequent to the completion of the present invention, Unexamined Patent Publication No. Hei 2(1990)-308489 (hereinafter called “prior art 1”), Unexamined Patent Publication No. Hei 9(1997)-205182 (corresponding to U.S. Pat. No. 5,793,664 and hereinafter called “prior art 2”), and Unexamined Patent Publication No. Hei 10(1998)-178158 (corresponding to U.S. Pat. No. 5,949,697 and hereinafter called “Prior art 3”), which are considered to be related to the technical subject matter of the present invention, were discovered. The prior art 1 discloses an arrangement wherein intermediate amplifiers (sub amplifiers) are provided outside each of a plurality of memory cell arrays. The prior art 2 discloses an arrangement wherein N channel type MOSFETs and P channel type MOSFETs of a sense amplifier control circuit are distributively disposed at a cross portion where a sense amplifier row and a sub-word driver column intersect. The prior art 3 discloses an arrangement wherein switch means for connecting GIO (Global Input/Output lines) and LIO (local Input/Output lines) brought into a hierarchical structure are distributively disposed in a conjunction area where a sense amplifier row (sense amplifiers) and a sub-word driver column intersect, and pairs of P channel type driver MOSFETs and N channel type driver MOSFETs of the sense amplifiers are disposed in the same conjunction area. However, none of these publications discloses or gives any consideration to a hierarchical IO structure according to the present invention, which is to be described later in this application.